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CY7C1021BNV33
64K x 16 Static RAM
Features
* 3.3V operation (3.0V-3.6V) * High speed -- tAA = 10, 12, 15 ns * CMOS for optimum speed/power * Low Active Power (L version) -- 576 mW (max.) * Low CMOS Standby Power (L version) -- 1.80 mW (max.) * Automatic power-down when deselected * Independent control of upper and lower bits * Available in 44-pin TSOP II and 400-mil SOJ * Available in a 48-Ball Mini BGA package
Functional Description[1]
The CY7C1021BNV is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BNV is available in 400-mil-wide SOJ, standard 44-pin TSOP Type II, and 48-ball mini BGA packages.
Logic Block Diagram
DATA IN DRIVERS
Pin Configurations
SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A7 A6 A5 A4 A3 A2 A1 A0
64K x 16 RAM Array 512 X 2048
I/O1-I/O8 I/O9-I/O16
COLUMN DECODER BHE WE CE OE BLE
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
ROW DECODER
Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation Document #: 001-06433 Rev. **
A8 A9 A10 A11 A12 A13 A14 A15
*
SENSE AMPS
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 1, 2006
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CY7C1021BNV33
Selection Guide
-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial Industrial Commercial/Industrial L 10 160 180 5 0.5 -12 12 150 170 5 0.5 -15 15 140 160 5 0.5
Pin Configurations
Mini BGA (Top View)
1
BLE
2
OE
3
A0
4
A1
5
A2 CE I/O2
6
NC I/O1 I/O3
A B C D E F G H
I/O9 BHE I/O10 I/O11
A3
A5
A4
A6 A7 NC
VSS I/O12 NC VCC I/O13 NC I/O15 I/O14 A14 I/O16 NC NC A8 A12 A9
I/O4 VCC I/O5 VSS I/O7
A15 I/O6 A13 A10
WE I/O8 A11 NC
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ......................................-0.5V to VCC+0.5V DC Input Voltage[1] .................................. -0.5V to VCC+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10%
Electrical Characteristics Over the Operating Range
-10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Test Conditions Min. 2.4 0.4 2.2 -0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT=0mA Com'l f = fMAX = 1/tRC Ind'l -1 -1 VCC+0.3V 0.8 +1 +1 160 120 40 2.2 -0.3 -1 -1 Max. Min. 2.4 0.4 VCC+0.3V 0.8 +1 +1 150 170 40 2.2 -0.3 -1 -1 Output HIGH Voltage VCC = Min., IOH = -4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current -12 Max. Min. 2.4 0.4 VCC+0.3V 0.8 +1 +1 140 160 40 -15 Max. Unit V V V V A A mA mA mA
Automatic CE Max. VCC, CE > VIH, Powerdown Current VIN > VIH or VIN < VIL, --TTL Inputs f = fMAX Automatic CE Power Down Current --CMOS Inputs Max. VCC, CE > VCC-0.3V, L VIN > VCC -0.3V or VIN <0.3V, f = 0
ISB2
5 500
5 500
5 500
mA A
Capacitance[2]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz Max. 6 8 Unit pF pF
AC Test Loads and Waveforms
3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 351 R 317 R 317 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 167 OUTPUT Equivalent to: THEVENIN EQUIVALENT 30 pF 1.73V R2 351 GND
Rise Time: 1 V/ns
3.0V 10%
ALL INPUT PULSES 90% 90% 10%
Fall Time: 1 V/ns
Note: 1. Minimum voltage is -2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Switching Characteristics[3] Over the Operating Range
-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low
[4, 5]
-12 Max. Min. 12 10 12 3 10 4 12 6 0 5 6 3 5 6 0 12 5 12 6 0 5 6 12 9 8 0 0 8 6 0 3 5 6 8 9 15 10 10 0 0 10 8 0 3 0 0 3 0 3 Max. Min. 15
-15 Max. Unit ns 15 15 7 7 7 15 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns ns
Description
Min. 10 3
0 3 0
Z[5]
CE HIGH to High Z[4, 5] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z CYCLE[6] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[5] WE LOW to High Z[4, 5] Byte Enable to End of Write 8 10 8 7 0 0 8 6 0 3 0
Data Retention Characteristics Over the Operating Range (L version only)
Parameter VDR ICCDR tCDR[8] tR
[9]
Description VCC for Data Retention Data Retention Current Com'l
Conditions[7] VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
Min. 2.0
Max. 100
Unit V A
Chip Deselect to Data Retention Time Operation Recovery Time
0 tRC
ns ns
Notes: 3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. No input may exceed VCC + 0.5V. 8. Tested initially and after any design or process changes that may affect these parameters. 9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes: 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13, 14]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes: 13. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9-I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Ordering Information
Speed (ns) 10 12 15 Ordering Code CY7C1021BNV33L-10VXC CY7C1021BNV33L-10ZXC CY7C1021BNV33L-12ZC CY7C1021BNV33L-12ZXC CY7C1021BNV33L-15ZC CY7C1021BNV33L-15ZXC CY7C1021BNV33L-15VXC CY7C1021BNV33L-15BAI CY7C1021BNV33L-15VXI CY7C1021BNV33L-15ZXI CY7C1021BNV33L-15ZI Package Diagram 51-85082 51-85087 51-85087 51-85087 51-85087 51-85087 51-85082 51-85096 51-85082 51-85087 51-85087 Package Type 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead TSOP Type II (Pb-free) 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-free) 44-Lead (400-Mil) Molded SOJ (Pb-free) 48-ball Mini Ball Grid Array (7 mm x 7 mm) 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead TSOP Type II (Pb-free) 44-Lead TSOP Type II Industrial Operating Range Commercial
Please contact local sales representative regarding availability of these parts.
Package Diagrams
48-ball FBGA (7 mm x 7 mm x 1.2 mm) (51-85096)
TOP VIEW
BOTTOM VIEW PIN 1 CORNER O0.05 M C O0.25 M C A B O0.300.05(48X)
PIN 1 CORNER (LASER MARK) 12 A B C 7.000.10 5.25 D E F G H 7.000.10 0.75 3 4 5 6
6
5
4
3
2
1 A B C D E
2.625
F G H
A
A
1.875 0.75
B
7.000.10 3.75 B 7.000.10
0.530.05
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85096-*F
SEATING PLANE 0.36 C
1.20 MAX.
Document #: 001-06433 Rev. **
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CY7C1021BNV33
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ (51-85082)
51-85082-*B
44-Pin TSOP Type II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06433 Rev. ** Page 9 of 10
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1021BNV33
Document History Page
Document Title: CY7C1021BNV33 64K x 16 Static RAM Document Number: 001-06433 REV. ** ECN NO. 423847 Issue Date See ECN Orig. of Change NXR Description of Change New Data Sheet
Document #: 001-06433 Rev. **
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